1. Field of the Invention
This invention relates to a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels.
The invention further relates to a multilevel memory device of the type comprising a plurality of multilevel memory cells.
The invention relates, particularly but not exclusively, to a Flash memory device, and the following description is made with reference to this application field with the only aim of simplifying its exposition.
2. Description of the Related Art
As it is well known in the field of Flash memories, the multilevel technique is widely accepted at present as a means to increase data density, with an equal physical density of the memory cells.
Known are in fact multilevel memory devices which can store plural logic values in a single memory cell. These devices are made in the form of integrated electronic circuits, which have achieved a sufficient degree of reliability to grant large scale production for several technical and commercial applications.
The market of semiconductor integrated electronic devices is showing great interest in multilevel memory devices because they afford information storage densities which are at least twice higher than those of two-level memory devices, either with the same technology and circuit area occupation.
The operation of such multilevel memory devices will now be briefly reviewed. The different programming state of a memory cell reflects in a different value of its threshold voltage Vth.
Of course, in the instance of a two-level cell, there would be only two values, corresponding to a logic 0 and a logic 1 state. In this case, the amount of information that can be stored results equal to one bit per cell.
On the other hand, a multilevel memory cell can store a larger number of bits than one. From the electrical standpoint, this means that there may be more than two possible threshold voltage values. The amount of information that can be stored in a single multilevel cell increases according to the following relation:
Number of bits per cell=log2(number of values of Vth) 
From the physical standpoint, the ability of altering the threshold voltage Vth, and therefore to program the multilevel memory cell, is granted by the floating gate design of the transistor which realizes the memory cell. The gate region is DC-isolated but can be accessed by charge injection processes of the Channel Hot Electrons and/or Fowler-Nordheim Tunneling Effect types.
When suitably controlled, these processes allow the amount of charge caught in the floating gate to be modulated, thereby allowing the effect of the latter on the threshold voltage value Vth to be changed.
The possibility of generating, in a large number of cells, a set of threshold voltage levels which can be distinguished upon reading is utilized to increase the density of the stored data.
However, the multilevel technique has inherently the disadvantage of slowing the processes of reading and programming each cell.
Also, there are applicationsxe2x80x94e.g. the implementation of a FAT memory for disk-on-silicon embodimentsxe2x80x94which require the writing of small amounts of data, usually at non-contiguous addresses, for which the programming times are significantly longer.
In these applications, data updating requires that erasing/programming cycles be executed. In view of the time taken by such operations, two major problems stand out:
the updating time per bit becomes unacceptable whenever the amount of data to be updated is small; and
an auxiliary memory is needed to store up data not to be updated, which data are nevertheless bound to become erased, since a whole sector would be erased at one time.
These problems make the use of current Flash memory architectures improposable.
Furthermore, power consumption is critical to such applications: all the energy used to store data which require no updating, and yet are affected by the erasing/programming process, is lost with respect to the updating operation.
Power usage is the more inefficient the smaller is the ratio between the data to be updated and the sector size.
The U.S. Pat. No. 5,936,884 granted on Aug. 10, 1999 in the name of Hasbun et al. describes a method for performing multiple writes before erasing a memory cell, using the multilevel technique, and hence the possibility of generating a set of threshold voltage levels in a large number of Flash cells, which voltage levels can be distinguished during a reading operation.
In particular, according to this known method, M bits are stored in a first group of levels of a multilevel memory cell and M superseding bits are stored in a second group of levels of the multilevel memory cell without erasing the cell itself. A group indicator is adjusted to identify a subsequent group of levels of the multilevel memory cell.
According to the known method described in the U.S. patent to Hasbun et al., the levels are xe2x80x9csuperimposedxe2x80x9d, i.e. the high level of a group is made to coincide with a low level of a subsequent group.
Thus, according to such a known solution, only Nxe2x88x921 levels of a total number N of levels are used to perform the reprogramming without erasing operations.
Moreover, to determine the value stored in a given multilevel memory cell, it is necessary to know what the last level written was, i.e. a tracking mechanism is needed. The group indicator described in the above cited U.S. patent provides for such a tracking mechanism to keep track of the current level or the proper reference voltage to use.
The degree of which tracking is performed (i.e. cell by cell, block, groups of blocks or device levels) is known as the tracking resolution.
The U.S. patent to Hasbun et al. states that a tracking mechanism implemented on a cell by cell basis might be inefficient. Moreover, when considering Flash memory devices, since all Flash cells within a block must be erased anyway, tracking might prove to be most efficient at the block or even the device level.
It should be noted that, contrary to what stated in such a known Patent, a group indicator on a block by block basis, or block indicator, increases the number of erasing executed for each cell. In fact, the bigger the block size, the greater the probability upon subsequent programming operations that the block indicator reaches the maximum value, thus requiring the sector, and hence the block, to be erased.
Even advantageous under various aspects, the above described known solution has a main drawback, connected to the tracking mechanism. In fact, the need of a tracking mechanism as a group indicator increases the complexity of the programming method for multilevel memory cells as well as of the corresponding multilevel memory device.
An embodiment of the present invention is directed to a simplified method of programming Flash memory cells, which method has structural and functional features able to simplify the programming without erasing mechanism, thereby overcoming the drawbacks with which methods of programming memory devices, according to the prior art, are beset.
The simplified method performs multiple reprogramming without erasing and does not require a tracking mechanism to keep track of the current level being programmed.
In particular, the programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels, comprises the phases of:
initially programming a cell threshold value to a first set of levels [0;(mxe2x88x921)] being m a submultiple of the plurality of levels of the multilevel cell;
reprogramming without erasing another set of levels [m;(2mxe2x88x921)] containing the same number m of levels as the first set;
reiterating the reprogramming without erasing phase until the levels of the multilevel cell are all exhausted.
Another embodiment of the present invention is directed a multilevel memory device comprising a memory array including a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units, a data updating operation being performed in parallel, wherein said data units are programmed by a programming method which comprises the phases of:
initially programming a cell threshold value to a first set of levels [0;(mxe2x88x921)] being m a submultiple of the plurality of levels of the multilevel cell;
reprogramming without erasing another set of levels [m;(2mxe2x88x921)] containing the same number m of levels as the first set;
reiterating the reprogramming without erasing phase until the levels of the multilevel cell are all exhausted,
wherein the maximum number of possible reprogrammings is univocally fixed by the threshold level of the cell.
A further embodiment is directed to a multilevel memory device comprising a memory array including a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units, a data updating operation being performed in parallel, further comprising at least a first sector and a second sector, which is an updated copy of the first one, both sectors being organized into data units programmed by a programming method which comprises the phases of:
initially programming a cell threshold value to a first set of levels [0;(mxe2x88x921)] being m a submultiple of the plurality of levels of the multilevel cell;
reprogramming without erasing another set of levels [m;(2mxe2x88x921)] containing the same number m of levels as the first set;
reiterating the reprogramming without erasing phase until the levels of the multilevel cell are all exhausted,
wherein the sectors are associated to a first programmed-unit counter and a second exhausted-unit counter, the first counter counting up each time that a first programming is effected in a data unit of the associated sector, and the second counter counting up upon any cell of a data unit of the associated sector reaching the maximum number of possible reprogrammings.
The features and advantages of the programming method and multilevel memory devices according to the invention will be apparent from the following description, of embodiments thereof, given by way of example and not of limitation with reference to the accompanying drawing.